1. Field of the Invention
The present invention relates to a delay time calculating device required for semiconductor logic verification, particularly for logic verification in back annotation of actual wiring information from layout data.
2. Description of the Background Art
FIG. 26 is a block diagram showing respective means forming a conventional delay time calculating device for back annotation of actual wiring information (parasitic wiring resistance and capacitance) from circuit connection data and layout data to calculate a delay time, and input/output information thereof.
As shown in FIG. 26, LSI circuit connection data D1 for specifying an LSI circuit to be verified by describing cells having predetermined logic functions and connection therebetween is applied to a C/RC model extracting means 1, a wiring delay element inserting means 4, a C model delay calculating means 7, and a C model associated detailed delay logic simulation 61 by an LSI circuit connection data providing means not shown.
Layout data D2 specifying a layout pattern of the LSI circuit corresponding to the LSI circuit connection data D1 is applied to the C/RC model extracting mean 1 by layout data providing means not shown.
The C/RC model extracting means 1 extracts lines for interconnecting cells and parasitic wiring resistances and capacitances serving as loads upon the lines from the LSI circuit connection data D1 and the layout data D2. The C/RC model extracting means 1 then outputs to the C model delay calculating means 7 a C model output result D3 having a predetermined file format in which only the parasitic wiring capacitances among the extracted wiring resistances and capacitances correspond respectively to a plurality of output lines carrying output signals from a plurality of cells in the LSI circuit specified by the LSI circuit connection data D1, and outputs to an RC model delay calculating means 8 an RC model output result D4 having a predetermined file format in which the parasitic wiring resistances and capacitances correspond respectively to the plurality of output lines.
The wiring delay element inserting means 4 inserts wiring delay elements into all signalling lines lying in the LSI circuit specified by the LSI circuit connection data D1 to output wiring delay element inserted LSI circuit connection data D7 to the RC model delay calculating means 8.
A cell-by-cell delay parameter library D8 having data groups specifying the delay time cell by cell is applied to the C model delay calculating means 7 and the RC model delay calculating means 8 by a cell-by-cell delay parameter library providing means not shown.
The C model delay calculating means 7 calculates a delay value for each cell by using an existing capacitance dependent delay calculating formula on the basis of the LSI circuit connection data D1, the C model output result D3, and the cell-by-cell parameter library D8, and then outputs C model associated delay value data D14 to the C model associated detailed delay logic simulation 61.
The RC model delay calculating means 8 calculates a delay value for each cell having a function and each wiring delay element by using an existing resistance and capacitance data dependent delay calculating formula on the basis of the RC model output result D4, the wiring delay element inserted LSI circuit connection data D7, and the cell-by-cell delay parameter library D8, and then outputs RC model associated delay value data D15 to an RC model associated detailed delay logic simulation 62.
The C model associated detailed delay logic simulation 61 executes detailed delay logic simulation associated with a C model on the basis of the LSI circuit connection data D1 and the C model associated delay value data D14.
The RC model associated detailed delay logic simulation 62 executes detailed delay logic simulation associated with an RC model on the basis of the wiring delay element inserted LSI circuit connection data D7 and the RC model associated delay value data D15.
FIG. 27 is a flow chart showing a delay calculating method associated with the C model. Referring to FIG. 27, the C/RC model extracting means 1 extracts the lines for interconnecting the cells and the parasitic wiring capacitances serving as loads upon the lines from the LSI circuit connection data D1, and outputs the C model output result D3 to the C model delay calculating means 7 in the step S31.
In the step S32, the C model delay calculating means 7 calculates the delay value for each cell by using the existing capacitance dependent delay calculating formula on the basis of the LSI circuit connection data D1, the C model output result D3, and the cell-by-cell delay parameter library D8, and then outputs the C model associated delay value data D14 to the C model associated detailed delay logic simulation 61.
FIG. 28 is a flow chart showing a delay calculating method associated with the RC model. Referring to FIG. 28, the C/RC model extracting means 1 extracts the lines for interconnecting the cells and the parasitic wiring resistances and capacitances serving as loads upon the lines from the LSI circuit connection data D1, and outputs the RC model output result D4 to the RC model delay calculating means 8 in the step S41.
In the step S42, the wiring delay element inserting means 4 inserts the wiring delay elements into all signalling lines lying in the LSI circuit specified by the LSI circuit connection data D1, and outputs the wiring delay element inserted LSI circuit connection data D7 to the RC model delay calculating means 8.
In the step S43, the RC model delay calculating means 8 calculates the delay value for each cell having a function and each wiring delay element by using the existing resistance and capacitance data dependent delay calculating formula on the basis of the RC model output result D4, the wiring delay element inserted LSI circuit connection data D7, and the cell-by-cell delay parameter library D8, and outputs the RC model associated delay value data D15 to the RC model associated detailed delay logic simulation 62.
In the conventional delay time calculating device as above constructed, the delay calculating flow is divided into the flow in which all signals are associated with the C model as shown in FIG. 27 and the flow in which all signals are associated with the RC model as shown in FIG. 28.
The former flow associated with the C model, in which the wiring delay elements are not added, permits high-speed delay time calculation and detailed delay logic simulation, but is disadvantageous in that, in terms of size reduction in future, consideration is not given to resistance elements, resulting in increased delay accuracy errors.
The latter flow associated with the RC model has no problem with respect to the delay accuracy since the accuracy is increased. However, it takes time to calculate the delay time because of insertion of the wiring delay elements into all signals, resulting in impractical simulation speeds.